Timing Parameters

Timing Parameters

The specifications for PC-133 and for DDR-RAM dictate the required timing parameters. The chips are sometimes quoted according to their most important timing parameters. The times (in clock cycles) refer to one of the following. (Definitions of the timing parameters are provided below.)

t_CL - t_RCD - t_RP
t_CL - t_RCD - t_RP - t_RAS
t_CL - t_RCD - t_RP - t_RAS - T1

For example, a common timing of a PC-133 RAM chip is 3-2-2 or 2-2-2. A common timing of a DDR-266 RAM chip is 2.5-3-3-6 and a common timing of a DDR-333 chip is 2.5-3-3-7. The DDR specifications allow for either 2.5 or 2.0 CL for the first timing parameter.

Recall that DDR stands for Double Data Rate. Hence, DDR-266 timings refer to the number of 133 MHz clock cycles. Similarly, DDR-333 timings refer to the number of 167 MHz clock cycles. In particular, if t_CL is 2.5 for 2.5-3-3-6 DDR-266, then t_CL (or more accurately, t_CAC) is guaranteed to be no more than 2.5/(133 MHz) = 18.8 ns and t_RCD is guaranteed to be no more than 3/(133 MHz) = 22.5 ns. The actual timing specs are:

DDR-266: T_CAC=15ns, t_RCD=20ns, t_RP=20ns, t_RAS=45ns
DDR-333: T_CAC=20ns, t_RCD=18ns, t_RP=18ns, t_RAS=42ns

A read or write access passes through three stages internally on the chip.

1. RAS (row access strobe): read row address
2. RAS-to-CAS: decode the row address, the sense amps (sense amplifiers) must have been precharged if new row requested
3. CAS (column access strobe): read selected columns and send to data pins (or write to data pins)

Some of the timings are defined as:

1. t_RP (Time for Row Precharge): time to charge sense amps, activate bank; Command to same bank must wait at least t_RP after PRECHARGE command
2. t_RCD (Time for Ras to Cas Delay): internal row signal settles enough for sensor to amplify it; earliest time to issue a READ or WRITE command after ACTIVE (round up to next full clock cycle, since commands are issued only on rising edge of clock signal)
3. t_RC (Time for Row Cycling): minimum time interval between successive ACTIVE commands to same bank; sum of t_RAS + t_RP
4. t_RRD (time for Ras to Ras Delay ?): minimum time interval between successive ACTIVE commands to different banks
5. t_CAC (Column Access ... / CAS Latency): data appears on output pins (see t_CL, below)
6. t_RAS (Time for activation / RAS Active Strobe(?)): time to activate a row of a bank (minimum time bank stays open before it can be closed/precharged again)
7. t_CLK: clock cycle time (also known as t_CK)
8. t_CL (CAS latency): t_CAC/t_CLK
9. t_DQSS (Time for Data Clock ... Strobe ?): Minimum time interval between WRITE command and valid data (nominally 1 clock cycle)
10. t_WTR (Time for Write To Read ?): Minimum time interval between end of WRITE and READ command (1 clock cycle)
11. t_WR (time for Write to Row Precharge ?): Minimum time interval between end of WRITE and PRECHARGE command (2 clock cycles)